The present invention relates to the processing of wafers in semiconductor manufacturing. More particularly it relates to apparatus and methods for eliminating unwanted native oxide growth when transporting wafers in a semiconductor manufacturing line. It also relates to preventing wafer slip during heating or cooling steps.
The manufacturing of semiconductor devices, such as integrated circuits and the like, involves subjecting a silicon wafer to numerous process steps using a variety of different apparatus. Great care is required to ensure that the wafer is not exposed to unwanted influences, like dust particles, particular chemical reactants, or unwanted extremes in temperature and humidity. Accordingly, the wafer is typically transported in a box to each different apparatus in a clean-room environment which has a controlled atmosphere.
One of the more daunting problems in the processing of silicon wafers in semiconductor manufacturing is the growth of unwanted oxide on the wafer surface while the wafer is being transported between processing apparatus. For many of the process steps, a pure silicon surface is required. Yet, when such a surface is exposed to air, a native oxide layer inevitably forms thereon.
This problem is presently addressed by subjecting a wafer either to a dry thermal process in a reducing environment or a wet chemical dip immediately before the processing step which requires an oxide free wafer surface. However, in the case of a dry thermal reduction, the process is typically performed at temperatures of about 1000xc2x0 C. or greater.
Unfortunately, such prolonged exposure to high temperature can result in excess diffusion of the structures formed in or on the silicon, and prevents the formation of shallow junctions, which are desirable in state-of-the-art devices. In other cases, when the next process is an LPCVD furnace deposition or anneal, there is presently no way to perform the oxide reducing step and then transport the wafer to the LPCVD furnace without exposing the wafer to air. Accordingly, during the transportation step, an oxide layer, whose thickness is proportional to the amount of time exposed to air, is formed.
Correspondingly, in the case of wet surface cleaning, a time window must be imposed between the wet process and the subsequent processing step requiring the clean surface in order to avoid formation of a native oxide.
Another problem associated with wafer processing is called xe2x80x9cwafer slip,xe2x80x9d which is a displacement of the crystal planes when a sufficiently large thermal gradient is created across a wafer. As LPCVD and oxidation/anneal furnaces are batch systems, there is no active cross-wafer temperature control. During a heating step of a batch of wafers, because heat flows from heating coils located outside the batch of wafers, outside edges of the wafers heat up before center regions of the wafers. Similarly, during cooling, outside edges of the wafers cool before center regions. The uneven heating or cooling provides the thermal stress which can induce wafer slip if the magnitude of thermal stress is sufficient. Therefore, batch apparatus can induce wafer slip if ramping up or ramping down the temperature is performed at too high a rate of temperature change. Certain single wafer rapid thermal process tools (RTP) address this problem by providing cross-wafer temperature control during temperature ramp-up and ramp-down. In some cases this is accomplished with a thermal chuck contacting the entire back surface of the wafer that provides for more uniform heating or cooling. Alternatively, individual lamps or groups of lamps can be controlled to provide for more uniform cross wafer heating or cooling. However, as mentioned above, the RTP tools are single wafer tools which can greatly reduce wafer throughput for processes that require a very long hot process step, such as a long anneal, deposition, or oxidation.
U.S. Pat. Nos. 5,380,682 and 5,259,881 issued to Edwards et al. (xe2x80x9cthe Edwards patentsxe2x80x9d) disclose a wafer processing cluster tool having a wafer batch pre-heating module that preheats all wafers in a batch. At the completion of the pre-heating, the wafers are transported through a load-lock one by one. A rapid thermal anneal station then heats the wafer to high temperature.
U.S. Pat. No. 5,271,732 to Yokokawa (the ""732 patent) discloses a heat treatment apparatus for wafers which includes a load-lock chamber, and which allows for flow of treatment gas within the environment.
The present invention relates to the processing of wafers in semiconductor manufacturing, and in particular relates to apparatus and methods for eliminating unwanted native oxide growth when transporting wafers in a semiconductor manufacturing line and preventing wafer slip during heating or cooling steps of a particular process. This is accomplished in this invention by processing at fixed temperature in a batch mode and ramping temperature in a single wafer processing mode. In one embodiment a rapid thermal cleaning process is combined with a batch oxidation, deposition, or anneal process.
Accordingly, a first aspect of the invention is a multi-chamber tool comprising a first hot process chamber and a second hot process chamber. The tool also includes a temperature controlled wafer handler for transporting a wafer from the first hot process chamber to the second hot process chamber.
A second aspect of the invention is a system for processing wafers comprising a first chamber for single wafer processing and a second chamber for batch processing. The tool also includes a wafer handler system for moving a wafer from the first chamber to the second chamber.
A third aspect of the invention is a wafer processing tool, comprising a batch processing fixture for batch processing a plurality of wafers at a first elevated temperature. The batch of wafers is not cooled from that elevated temperature within the batch processing fixture. The tool also includes a first single wafer processing apparatus for rapidly cooling a wafer of the batch of wafers without first heating the wafer from the first elevated temperature. The single wafer processing apparatus includes a chuck to maintain a uniform temperature across the wafer during cooling.
A fourth aspect of the invention is a wafer processing tool, comprising a batch processing fixture for batch processing a plurality of wafers at a first elevated temperature. The batch of wafers is not substantially ramped in temperature within the batch processing fixture. The tool also includes a single wafer processing apparatus for rapidly ramping temperature of a wafer of the batch of wafers from the first elevated temperature. The single wafer processing apparatus also includes a chuck to maintain a uniform temperature across the wafer during the ramping.
A fifth aspect of the invention is a method of processing wafers. The method includes the step of providing a batch of wafers in a batch processing fixture for batch processing the wafers at a first elevated temperature. The next step is moving a wafer of the batch to a single wafer processing apparatus. The next step is rapidly cooling the wafer, wherein a uniform temperature across the wafer is maintained during the cooling. There is no rapid heating step between the batch processing step and the rapid cooling step.
A sixth aspect of the invention is a method of processing wafers. The method includes the step of providing a batch of wafers in a batch processing fixture for batch processing the wafers at a first elevated temperature. The batch of wafers is not substantially ramped in temperature within the batch processing fixture. Next a wafer of the batch is moved to a single wafer processing apparatus for ramping in temperature from the elevated temperature. The next step is rapidly ramping the temperature of the wafer from the first elevated temperature, wherein a uniform temperature across the wafer is maintained during the ramping.
A seventh aspect of the invention is a method of processing wafers. The method comprises the steps of first, placing a wafer on a pedestal and rapidly heating the wafer in a reducing environment to remove oxide from the wafer, then removing the wafer from the pedestal and placing the wafer in an inert or reducing environment in a cassette surrounded by an isothermal chamber, then, when the cassette has a desired number of wafers stored therein, thermally processing the wafers stored therein, then removing the wafers from the cassette and placing each wafer in an inert or reducing environment on a pedestal pre-heated to match the temperature of the wafer, and then finally rapidly cooling the wafer.
An eighth aspect of the invention is a method of processing wafers. The method comprises the step of placing each wafer one at a time on a pedestal and rapidly heating the wafer in a reducing environment to remove oxide from the wafer. Next cooling each wafer one at a time to a predetermined temperature in an inert or reducing environment. Then transferring each wafer one at a time to a cassette located in an inert or reducing environment so that each wafer in the cassette is at substantially the same temperature. Then thermally processing the wafers in the cassette.